1. Field of the Invention
The present invention relates to an integrated circuit (IC). More precisely, it relates to a package for an ultra high speed IC.
2. Description of the Related Art
FIGS. 12 and 13 show a known IC package, wherein FIG. 12 is a perspective view of a known IC package and FIG. 13 is a cross sectional view taken along the line X--X' in FIG. 12. In FIGS. 12 and 13, an integrated circuit (or IC chip) 1 is incorporated in the package and is electrically connected to an external circuit 3 through an external connecting terminal portion 2. The connecting terminal portion 2 has a dielectric alumina frame 5 secured to a metal substrate 4 made of copper or the like, and connecting conductor patterns 6a, 6b, and 6c provided on the alumina frame 5. An alumina frame 8 having a sealing conductor ring 7 coated on the rear face (upper face in FIG. 13) thereof, is placed on the conductor patterns 6b. The conductor patterns 6b are formed by coating the alumina frame 5 with a tungsten paste. The conductor patterns 6b are plated with Nickel (Ni) and gold (Au) and form conductor patterns 6b, 6a and 6c in contact with the bottom face (FIG. 13) and on opposite sides of the alumina frame 8, respectively. The outer conductor patterns 6c are connected to the leads 9, which are connected to the external circuit 3. The inner conductor patterns 6a are connected to the IC 1 by means of lead wires 61.
The conductor ring 7 is formed by metallizing the upper surface of the alumina frame 8 and then plating it with Ni and Au, similar to the conductor patterns 6b. Accordingly, the conductor patterns 6b form a laminate structure together with the alumina frames 5 and 8.
FIG. 14 is a longitudinal sectional view of an IC package shown in FIG. 12, showing a parallel arrangement of the conductor patterns 6 when located side by side.
In the IC package having the external connecting terminal portion of the prior art shown in FIGS. 12-14, the connecting conductor patterns 6b and the sealing conductor pattern 7 are electromagnetically connected through the alumina (alumina frame 8) having a relative dielectric constant of 9.6, thus resulting in the occurrence of a resonance phenomenon. This is equivalent to an establishment of a connection between a line 9' of the conductor patterns 6b having a characteristic impedance Z.sub.0 and a ring resonant line 10 corresponding to the length of the conductor ring 7, so that the line 9' has a characteristic impedance different from Z.sub.0 in a certain frequency band, as shown in FIG. 15. As a result, signals input to the leads 9 from a signal source (not shown) having an impedance Z.sub.0 are reflected by the conductor pattern 6b, because of impedance irregularities. The reflected signals will cause a misoperation of the IC, particularly an ultra high speed IC.
In addition to the misoperation mentioned above, the side-by-side arrangement of the conductor patterns 6, as mentioned above causes the conductor patterns to be electromagnetically connected through the alumina (alumina frames 5 and 8), resulting in an undesirable cross talk, which can be considered electromagnetic interference.
The higher the frequency component of the high speed pulse signals, the larger the possibility of the occurrence of cross talk.
To solve the problems mentioned above, Japanese Unexamined Patent Publication (Kokai) No. 58-190046 teaches a modified arrangement as shown in FIG. 16, in which a metal housing 40 has through openings 40A in which corresponding connecting terminal units 31 are fitted. Each of the terminal units 31 has a dielectric substrate 29 which is provided, on its outer surface, with a laminated strip line 30 and a dielectric block 33 which is integral with the dielectric substrate 29 and which is placed on the strip line 30. Leads 9 are connected to the strip lines 30.
FIG. 17 shows steps for manufacturing the terminal units 31 of the arrangement shown in FIG. 16, in which a predetermined pattern of tungsten paste (corresponding to the strip 30) is formed on an alumina raw ceramic plate (corresponding to the substrate 29), as can be seen in FIG. 17(a). Subsequently, a smaller alumina raw ceramic plate (corresponding to the dielectric block 33) is located on the substrate 29, as shown in FIG. 17(b), and the assembly is then sintered. Then, as can be seen from FIG. 17(c), the pattern 30 is plated with Au, and the bottom and sides of the assembly (terminal unit 31) and the upper face of the smaller ceramic plate (dielectric block 33) are metallized.
With this arrangement, the strip 30 is split into two portions by the dielectric block 31, one of which portions is connected to an external circuit of the package through the lead 9 and the other strip portion (inner strip portion) being connected to an internal circuit (IC, etc.) of the package.
However, in the package shown in FIGS. 16 and 17, although the strip portions 30 are shielded by the metal housing, it is difficult to manufacture the electrical terminal units 31 in the manner shown in FIG. 17. This difficulty becomes greater in particular in the case of an IC package having a large number of terminals. Furthermore, it is impossible to prevent cross talk between the portions of the strips 30 located outside of the metal housing.
To solve this problem, there is also known an IC package as shown in FIG. 18. In FIG. 18, 40 designates the metal housing, 40A the through openings, 22 a cap, 9 the leads connected to the strips 30, and 29 the dielectric substrates of the terminal units 31. In the IC package shown in FIG. 18, metallized layers 25 are formed on the dielectric substrate 29, between the adjacent leads 9 to prevent cross talk between the terminals 9 (strip portions 30). However, in the arrangement shown in FIG. 18, it is difficult to form the metallized layers 25, and this arrangement is not suitable for the provision of the terminals at a high density. Also, since the metallized layers 25 are formed only on the surface of the dielectric substrate 29, an electromagnetic coupling can be produced through an inner portion of the dielectric substrate.
Furthermore, in the prior art, usually the leads 9 can be connected to the conductor patterns 6c by brazing or soldering, as shown at 100 in FIG. 12. However, in this soldering or brazing, no attention has been paid to the impedance irregularity mentioned above. Namely, the soldering or brazing materials 100 irregularly spread out of the leads 9 at the connections between the leads 9 and the conductor patterns 6c, and this has an adverse influence on the impedance regularity of the IC package.